This invention relates to a binary comparator configured as an integrated circuit and particularly to its capability of achieving higher calculation speeds by arranging given digits in a regular array.
FIGS. 5, 6, and 7 are a circuit diagram of a one digit comparator circuit, and a circuit diagram and a timing chart for a multiple digit comparator circuit, respectively.
FIG. 5 shows a one digit comparator circuit. The explanation below is for a positive logic unless otherwise indicated. A first input data A and a second input data B to be compared are entered in input terminals A and B. The first and second input data A and B are one digit binary numbers. An inverter 102 connected to the second input data B outputs an inverted signal. A NAND circuit 100 is connected to the first input data A and the inverter 102. An inverter 101 is connected to the output of the NAND circuit 100. A NOR cirucit 103 is connected to the input data A and the output of the inverter 102. A NOR circuit 104 has its input connected to the output of the NOR circuit 103 and the output of the inverter 101. A transfer gate 105 has its gate connected the output of inverter 101, its source connected to the power supply, and its drain connected to a carry output terminal CO. A transfer gate 106 has its gate connected to the output of NOR circuit 103, its source connected to GND, and its drain connected to the carry output terminal CO. A transfer gate 107 has its gate connected to the output of NOR circuit 104, its source connected to a carry input terminal CI and its drain connected to carry output terminal CO. This is the configuration of a one digit comparator circuit 200.
The operation of the one digit comparator circuit 200 is described below.
If A&gt;B then the first input data A is a "1" and the second input data B is a "0" and the following logic levels are generated: the output of the inverter 102 to which the second input data B is entered becomes "1", the output of the NAND circuit 100 becomes "0", the output of the inverter 101 becomes "1", the output of the NOR circuit 103 becomes "0", and the output of the NOR circuit 104 becomes "0". Accordingly, the carry output terminal CO outputs a "1" by turning transfer gates 106 and 107 "OFF" and by turning the transfer gate 105 "ON".
If A&lt;B, then the first input data A is a "0" and the second input data B is a "1" and the following logic levels are generated: the output of the inverter 102 to which the second input data B is entered becomes "0", the output of the NAND circuit 100 becomes "1", the output of the inverter 101 becomes "0", the output of the NOR circuit 103 becomes "1", the output of the NOR circuit 104 becomes "0". Accordingly, the transfer gates 105 and 107 are turned "OFF", the transfer gate 106 is turned "ON" and the carry output terminal CO outputs a "0".
If A=B, then the first input data A and the second input data B are both "1" or both "0" and the following logic levels are generated: the output of the inverter 101 becomes "0", the output of the NAND circuit 100 becomes "1", the output of the inverter circuit 101 becomes "0", the output of the NOR circuit 103 becomes "0", and the output of the NOR circuit 104 becomes "1". The carry output terminal CO assumes the same value as the carry input terminal CI by turning the transfer gates 105 and 106 "OFF", and by turning the transfer gate 107 "ON".
FIG. 6 shows a multiple digit (here a four digit) comparator based on the one digit comparator circuit 200 shown in FIG. 5. FIG. 7 is a timing chart for the comparator circuit of FIG. 6.
The symbols used in FIG. 5 are used for the same or corresponding parts of FIG. 6 and FIG. 7. In FIG. 6, A and B are four bit input data. The bits of the first input data A, viewed from the least significant bit (LSB), are assigned the names A0, A1, A2, and A3. The bits of the second input data B, viewed from the LSB, are assigned the names B0, B1, B2, and B3. The comparator circuit 200 is identical to the comparator circuit shown in FIG. 5.
A clock input CL is entered at the LSB carry input terminal CI0. Each of the carry input terminals CI (N) for the other digits is connected to the carry output terminal CO (N-1) for the previous stage (N is an integer between 1 and 3). An N channel transistor 201 has its source connected to the most significant bit (MSB) carry output terminal CO3 and its gate connected to the clock input CL. An inverter 202 is an input to the drain of the N channel transistor 201. An inverter 203 takes the output of the inverter 202 as its input. An inverter 204 takes the clock input CL as its input. An N channel transistor 205 has its source connected to the output of the inverter 203; its gate connected to the output of the inverter 204; and its drain connected to the input of the inverter 202. The inverters 202, 203, and 204, together with the N channel transistors 201 and 205 constitute a latch 210.
A strobe clock SCK is connected to the inputs of NOR circuits 207, 208 and 209. If the outputs of the inverter 206 and of the inverter 202 are connected to a NOR circuit 207, then, as shown in FIG. 7, the strobe clock SCK is entered and the output of the NOR circuit 207 goes to "1" since A&gt;B. If the output of the MSB carry output terminal CO3 and the output of the inverter 202 and the strobe clock SCK are inputted to a NOR circuit 208, then its output becomes "1" since A=B. If the output of the MSB carry output terminal CO3, the output of the inverter 203, and the strobe clock SCK are entered in the NOR circuit 209, then its output becomes "1" since A&lt;B.
The operation of the four digit comparator circuit is described below.
If when (A0, A1, A2, A3)=(0,0,1,0), (B0, B1, B2, B3)=(0,0,1,0) then each of the transfer gates 107 are turned "ON", and CI0=CO0=CI1=CO1=CI2=CO2=CI3=CO3. this means that the MSB carry output terminal CO3 becomes "1" during the first half of the clock input CL and that when the clock input CL changes from "1" to "0", the latch 210 is latched at "1". The latch 210 holds "1", the output of the inverter 202 becomes "0", the output of inverter 203 becomes "1" and the output of the NOR circuit 209 goes to "0" to show that A&lt;B. Moreover, if the clock input CL is "0", then 0=CI0=CO0=CI1=CO1=CI2=CO2=CI3=CO3, the output of inverter 206 becomes "1" and the output of the NOR circuit 207 becomes "0" to show that A&gt;B. The NOR circuit 208, by setting the MSB carry output terminal CO3 to "0", sets the output of the inverter 202 to "0" and the timing of the strobe clock SCK to "1" to show that A=B.
FIG. 7 shows the timing of the output of the NOR circuit 207, which indicates that A&gt;B, or of the output of the NOR circuit 209, which indicates that A&lt;B, when the first data output A and the second output B have various values and when the timing of the strobe clock SCK is "0".
Conventional comparators are configured as described above. Each digit of multiple digit comparators can be configured based on the single digit model. This configuration, however, which requires a latch 210, three input NOR circuits 207-209, and an inverter 206 in the last stage of the comparator circuit in order to output a signal determined by the relative magnitude of the two input data A and B has the drawbacks of an uneven layout, increased circuit size and a longer delay time.